The paper entitled “Performance Analysis Of Ultra Low-Voltage Rail-to-Rail Comparator In 130 nm CMOS Technology” has been published in the proceedings of the 2019 IEEE AFRICON!

This paper discusses a performance of an ultra low-voltage / low-power voltage bulk-driven comparator, designed and fabricated in standard twin-well 130 nm CMOS technology. The proposed circuit topology can handle the input voltage within rail-to-rail range and is capable of working in industrial temperature range from -20 to 85 ° C and with power supply voltage as low as VDD=0.4 V. It can also operate with three different levels of hysteresis, selected by 2-bit input digital code. The topology can be easily modified to contain enable feature and hence, mimic a behavior of dynamic (clocked) comparator. The measurement results obtained from fabricated prototype chips are presented and discussed as well. An excellent correlation between the post-layout simulations and the measured bench data has been observed. The presented novel silicon-proven topology has been successfully employed in power management unit and voltage regulation loop, voltage-to-frequency converter and opamp input offset calibration block.