The paper entitled “Autonomous On-Chip Digital Calibration for Analog ICs in Nanotechnologies” the paper entitled “Low-Leakage ESD Structures in 130nm CMOS Technology” and the paper entitled “Development of test equipment for evaluation of low-power AC/DC converter ASIC” have been published in the proceedings of the 30th DADIOELECTRONIKA 2020!

The first paper proposes implementation of on-chip digital calibration for a variable gain amplifier. It does not require additional setting or test, and therefore, it is autonomous. The calibrated amplifier can be used in continuous operation, while the `ping-pong’ technique is utilized. The prototype chip was fabricated in a standard 130 nm CMOS technology, and it operates under the supply voltage of 0.6 V. It is aimed at cancellation of VGA input offset voltage V IOFF . Implemented system was verified through Monte Carlo and corner analysis at the design phase. After fabrication the experimental measurements took place over 10 packaged samples. Its results quite well fits between corners of simulations. The measured calibrated VGA exhibits the input offset voltage from 13 μ V to 167 μV. In order to evaluate the contribution of implemented calibration method, the experimental measurements were also carried out over not calibrated VGA samples. These results reveal V IOFF μ = 403 μ V and σ = 3,45 mV.

The second paper addresses a non-standard ESD protection structures developed in general purpose 130 nm CMOS technology and modeled in VerilogA language for transistor-level circuit simulators. ESD structures represent an additional load to the on-chip circuits and can exhibit quite significant portion of the overall power consumption in low-voltage and low-power circuit designs. The paper describes and discuss the properties of ESD structures designed with minimized leakage current as the main design constraint, while still maintaining their protection capabilities. The other ESD structure discussed in this article was designed for negative voltage levels, which brings completely new possibilities in terms of the power supply voltage range and circuit design. The accuracy of developed VerilogA models is compared to experimental data obtained by laboratory measurement at room temperature and compact models provided by the foundry.

Finally, in the third paper, the authors extend their previous work, where they proposed an AC/DC conversion stage optimized for these conditions specifically. It offers higher power efficiency and lower no-load consumption when compared to existing designs. The proposed conversion stage was since implemented and manufactured in a high-voltage CMOS process. The aim of this paper is to describe the process of measurement and verification of the manufactured samples. The development of the necessary test hardware, in a form of dedicated printed circuit boards, is also included in this paper. As the testing of the converter integrated circuit is still ongoing, only preliminary results are included so far.